The Anti-Tamper Digital Clocks Diaries
The Anti-Tamper Digital Clocks Diaries
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The former description from the disclosed embodiments is furnished to permit any person experienced within the art to create or make use of the current invention. Various modifications to these embodiments will probably be commonly clear to Those people experienced within the art, as well as the generic concepts outlined herein can be placed on other embodiments with out departing from the spirit or scope on the invention.
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With even further reference to FIG. 7, A further aspect of the creation might reside in an equipment for detecting clock tampering, comprising: a primary circuit 750A, a primary plurality of resettable hold off line segments 710, a 2nd circuit 750B, a second plurality of resettable hold off line segments 720, and an Examine circuit 240. The main circuit offers a primary monotone sign during a primary clock Examine period of time connected to a clock. The first plurality of resettable hold off line segments Just about every delay the very first monotone signal to produce a respective initial plurality of delayed monotone alerts. Resettable delay line segments among a resettable delay line segment associated with a minimum amount delay time as well as a resettable hold off line section related to a maximum delay time are Every related Anti-Tamper Digital Clocks to discretely expanding hold off moments. The second circuit delivers a 2nd monotone signal for the duration of a 2nd clock Appraise time period connected to the clock.
a plurality of resettable hold off line segments that delay the monotone sign to generate a respective plurality of delayed monotone signals Every having both a a single or simply a zero logic benefit, wherein resettable hold off line segments among a resettable delay line phase connected with a minimum hold off time and a resettable hold off line segment connected to a greatest hold off time are Each and every associated with discretely increasing delay periods; and
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38. The equipment for detecting voltage tampering as outlined in assert 37, wherein the resettable delay line segments are reset throughout a reset time frame, whereby the reset period of time is before the Appraise period of time.
a primary plurality of resettable delay line segments that each hold off the main monotone sign to create a respective initial plurality of delayed monotone alerts, wherein resettable delay line segments among a resettable hold off line segment related to a minimum delay time plus a resettable delay line section connected with a maximum delay time are Just about every related to discretely increasing hold off occasions;
A monotone sign is presented through a clock Assess period of time associated with a clock. The monotone signal is delayed applying Each individual of the plurality of resettable hold off line segments to make a respective plurality of delayed monotone signals. The clock is used to trigger an Assess circuit that makes use of the plurality of delayed monotone signals to detect a clock fault.
Another element of the invention might reside within an equipment for detecting clock tampering, comprising: indicates 250 for providing a monotone signal 220 all through a clock Examine period of time 310 affiliated with a clock CLK; usually means 210 for delaying the monotone signal using a plurality of resettable delay line segments to make a respective plurality of delayed monotone indicators 230 acquiring discretely raising hold off times in between a least delay time along with a most hold off time; and signifies 240 for utilizing the clock CLK to trigger an evaluate circuit 240 that works by using the plurality of delayed monotone signals to detect a clock fault.
The current creation relates generally to detecting tampering While using the clock and/or supply voltage of the processor.